The present invention relates to a semiconductor device having a high breakdown voltage and a method for manufacturing the same.
Various structures have been studied in the prior art for a lateral semiconductor device with which the on-state resistance can be reduced while ensuring a high breakdown voltage. An example of such a semiconductor device is disclosed in U.S. Pat. No. 6,168,983, which will now be described with reference to the drawings.
FIG. 10 is a cross-sectional view illustrating a first semiconductor device disclosed in the U.S. patent.
As illustrated in FIG. 10, an n-type source region 14 and an n-type extended drain region 23 are formed with an interval therebetween in an upper portion of a p-type semiconductor substrate 16. A drain contact portion 19 electrically connected to a drain electrode 11 is formed in an upper portion of the extended drain region 23.
A p-type buried layer 18 is formed in the extended drain region 23 so as to extend substantially parallel to the substrate surface. Thus, in the extended drain region 23, an n-type upper layer region 24 is formed over the p-type buried layer 18 while an n-type lower layer region 25 is formed under the p-type buried layer 18.
A p-type substrate contact region 13 is formed in an upper portion of the semiconductor substrate 16 so as to be in contact with the source region 14, and the source region 14 and the substrate contact region 13 are both electrically connected to a source electrode 10.
A gate electrode 12 is formed on the semiconductor substrate 16, with a gate insulating film 20 being interposed therebetween, in an area between the source region 14 and the extended drain region 23, and a region of the semiconductor substrate 16 that is located under the gate electrode 12 functions as a channel region 28. The surface of the semiconductor substrate 16, including the gate electrode 12 formed thereon, is covered by an insulating film 27.
Thus, the first semiconductor device is characterized in that the n-type upper layer region 24 and the p-type buried layer 18 are provided within the n-type extended drain region 23.
Since the p-type buried layer 18 is set to the reference potential via the semiconductor substrate 16, the extended drain region 23 and the semiconductor substrate 16 are reversely biased, and the extended drain region 23 and the p-type buried layer 18 are also reversely biased, when a voltage is applied to the extended drain region 23. Therefore, a depletion layer expands from the junction between the extended drain region 23 and the p-type buried layer 18, while a depletion layer also expands from the junction between the extended drain region 23 and the semiconductor substrate 16. By utilizing the dielectric breakdown voltage of these depletion layers, it is possible to increase the breakdown voltage of a MOS transistor.
When a voltage is applied to the gate electrode 12, the channel region of the MOS transistor is turned conductive, and a drain inner current primarily flows through the extended drain region 23 while being divided into two flows, one through the n-type upper layer region 24 and the other through the n-type lower layer region 25, as indicated by broken lines. Therefore, in order to obtain a high breakdown voltage, the impurity concentration of the n-type lower layer region 25, which is located under the p-type buried layer 18 in the extended drain region 23, is reduced, so as to increase the size of the depletion layer that expands from the junction when a reverse bias voltage is applied.
In order to reduce the impurity concentration of the n-type lower layer region 25, the concentration of the doped impurity is reduced and the impurity is thermally diffused in the step of forming the extended drain region 23.
However, when the impurity concentration of the n-type lower layer region 25 is reduced, the on-state resistance increases. Therefore, it is not preferred that the impurity concentration of the n-type lower layer region 25 is reduced excessively. Thus, in order to reduce the on-state resistance while ensuring a high breakdown voltage, it is necessary to increase the impurity concentration of the n-type upper layer region 24, which is provided on the upper surface side.
However, when the impurity concentration of the n-type upper layer region 24 in the extended drain region 23 is high, the expansion of the depletion layer in the n-type upper layer region 24 upon application of the reverse bias voltage will be insufficient, thereby changing the electric field distribution and thus lowering the breakdown voltage. Therefore, it is not preferred to excessively increase the impurity concentration of the n-type upper layer region 24.
As described above, while the first semiconductor device aims at realizing both a reduced on-state resistance and a high breakdown voltage, they cannot be realized at the same time to a sufficient degree with the first semiconductor device.
The U.S. patent further discloses a second semiconductor device, in which another p-type buried layer is formed within the extended drain region 23 so as to extend substantially parallel to the substrate surface with an interval between the two p-type buried layers, in order to reliably reduce the on-state resistance while ensuring a high breakdown voltage. In this way, the breakdown voltage is improved without lowering the impurity concentration of the n-type lower layer region 25.
FIG. 11 is a cross-sectional view illustrating the second semiconductor device disclosed in the U.S. patent. As illustrated in FIG. 11, a first p-type buried layer 18A and a second p-type buried layer 18B are formed in the extended drain region 23. The first p-type buried layer 18A and the second p-type buried layer 18B below the first p-type buried layer 18A extend substantially parallel to the substrate surface and are spaced apart from each other in the depth direction.
In the second semiconductor device, the first p-type buried layer 18A and the second p-type buried layer 18B are formed in the extended drain region 23, whereby when a voltage that is a reverse bias to the semiconductor substrate 16 is applied to the extended drain region 23, a depletion layer expands from the junction between the extended drain region 23 and the first buried layer 18A, the junction between the extended drain region 23 and the second buried layer 18B, and the junction between the extended drain region 23 and the semiconductor substrate 16. Therefore, even if the impurity concentration of the n-type extended drain region 23 is set to be high, the depletion layers formed by the extended drain region 23 and the first and second buried layers 18A and 18B expand easily. Thus, it is possible to ensure a high breakdown voltage of the MOS transistor.
Moreover, when a current path is established between the extended drain region 23 and the source region 14, a current flows through the extended drain region 23 whose impurity is set to be high, whereby the on-state resistance can be reduced. In this way, it is possible to reliably reduce the on-state resistance while ensuring a high breakdown voltage.
The drain inner current of the MOS transistor flows while being divided into three separate flows respectively through the n-type upper layer region 24, an n-type intermediate layer region 26 and the n-type lower layer region 25 in the extended drain region 23, as indicated by broken lines in FIG. 11. Therefore, the resistance value of the extended drain region 23 of the MOS transistor can be represented by the parallel resistance value of the three-layer current path.
However, the second conventional semiconductor device as described above has the following problem. When forming the extended drain region 23, an n-type impurity, e.g., phosphorus (P) ion, is implanted and then thermally diffused so that the diffusion depth is about 5 μm to 15 μm. The ion implantation is performed with an implantation energy of about 100 keV to 150 keV. Therefore, while a surface region of the extended drain region 23 can be formed with a high concentration, the intermediate layer region 26 has a lower n-type impurity concentration, and the lower layer region 25 has an even lower n-type impurity concentration.
Therefore, the second conventional semiconductor device has a high resistance value in the intermediate layer region 26 and in the lower layer region 25 of the extended drain region 23, whereby the MOS transistor has an increased on-state resistance.